1. Field of the Invention
The present invention relates to the field of line drivers for digital circuits. Specifically, the present invention relates to a high-speed line driver that is optimal for driving compare lines within a content addressable memory unit.
2. Art Background
Content addressable memory is a type of memory that is accessed by requesting whether or not a particular piece of data is stored in the content addressable memory. For example, a circuit may place a data value on a bus coupled to a content addressable memory and ask the content addressable memory if it contains the data value placed on the bus. If the content addressable memory contains the requested data value, the content addressable memory generates a positive response on an output line.
Within a content addressable memory are n entries for storing data values. Each of the entries in the content addressable memory consists of m memory cells wherein m equals the width of the data stored in the content addressable memory. Each memory cell is connected to a compare line that carries input data. Each memory cell connected to a compare line loads the compare line with resistance and capacitance (RC loading). Therefore, to properly drive a compare line in an n entry content addressable memory, a compare line driver must provide sufficient current to drive the RC loading caused by the n memory cells coupled to the compare line.
FIG. 1 shows a typical prior art line driver circuit for driving compare lines in a content addressable memory. The prior art line driver circuit comprises a pair of NAND gates (81 and 82) for prebuffering and two pairs of conventional CMOS inverter circuits (91 and 93, 95 and 97) for driving the load on the CL and CL compare lines.
To construct a compare line driver using the prior art line driver circuit as illustrated in FIG. 1, the individual transistors (not shown) of the line driver circuit must be constructed large enough to provide sufficient current to drive the RC loading on the compare lines within the content addressable memory. Thus, to drive compare lines in a large content addressable memory array, prior art compare line drivers require a large amount of die layout area.
Furthermore, the output line of the prior art compare line driver circuit is static, meaning that in the compare line driver circuit's reset state, one compare line is high and the other compare line is low. In the next set phase of the circuit, the CL and CL compare lines may need to change logical states, and therefore go through a full voltage level swing. Since a full voltage level swing requires a complete voltage swing rise time and a complete voltage swing fall time, the typical prior art compare line driver is also slow.
Therefore, it would be desirable to construct a compare line driver that does not require large amount of die layout area. Furthermore, it would be desirable to construct a compare line driver that quickly drives the compare lines in a content addressable memory to the proper logic level such that the content addressable memory can provide a very fast response to the memory inquiry.